1. Field of the Invention
The present invention relates to an amplifying circuit and a wireless communications apparatus including the same.
2. Description of the Related Art
In a wireless communications system such as a mobile phone or a wireless data communications apparatus, an amplifying circuit for amplifying a received signal is installed on a signal-receiving side. A low noise amplifier (LNA) may be provided as an example of an amplifying circuit. An LNA is a circuit amplifying a signal by reducing noise generated in the circuit itself to the lowest possible level thereof, and thus is an essential circuit disposed at a front end of a wireless receiving circuit (please see Patent Document 1).
In the case of implementing an LNA using a complementary metal oxide semiconductor (CMOS), manufacturing costs of the LNA may be reduced. Therefore, demand for this scheme has increased. In addition, owing to the original role of an LNA, an LNA is required to constantly have a high degree of linearity so as to reduce a noise figure (NF) and remove an interference wave.
Meanwhile, in the case in which a CMOS LNA circuit is used for, for example, time division duplexing (TDD), it is necessary to block current from flowing to the CMOS LNA circuit while the CMOS LNA circuit is not operating during a transmission due to the requirement for a reduction in power consumption.
According to the related art, in order to block current from flowing to the single ended CMOS LNA circuit while the CMOS LNA circuit is not operating, a gate bias voltage of an input transistor of the LNA circuit (for example, a ground potential) is equalized with a source voltage at a bias circuit side.
However, the LNA circuit generally has large resistance and capacitance components present therein, due to a resistor connected between the gate voltage and a node of the bias circuit. In addition, a certain period of time, according to a time constant defined by the resistance and capacitance components, is required to change the gate bias voltage.
In the case in which the CMOS LNA circuit is used for time division duplexing, a problem in which the change of the gate bias voltage fails to be matched to a switching time of transmission and reception, may occur. In order to solve such a problem, a method of installing a switch at a front end of the input transistor of the LNA circuit has also been considered. However, in the case in which a switch is installed at the front end of the input transistor of the LNA circuit, there is a risk that the NF of the LNA will increase.